1. Field of the Invention
The present invention relates to a method for controlling memories such as DRAMs and its memory control circuit. In particular, the present invention relates to a technique for making it possible to control memories of a plurality of kinds differing in control system by using the same controller (memory control circuit).
2. Description of the Related Art
In the DRAM (dynamic random access memory) which is a representative memory, an SDRAM (synchronous DRAM) which conducts operation in synchronism with a clock supplied from the outside has become general. At present, however, the DDR (double data rate)-SDRAM based on the SDRAM which conducts data transfer not only at timing of a rising edge of the clock but also at timing of a falling edge has become the main stream (see, for example, JP-A-2000-173267). This DDR-SDRAM is also being gradually replaced by DDR2-SDRAM which is an improved version of the DDR-SDRAM. Furthermore, the FC (fast cycle)-DRAM which takes in a row address and a column address simultaneously (at consecutive clocks) is also proposed and provided for the market (see, for example, WO98/56004). Typically, the memory such as the DRAM executes an instruction issued by a high rank control unit such as a CPU via an LSI called controller.
On the other hand, in an application device such as a personal computer having a DRAM mounted thereon, it is necessary to provide a device obtained by mounting DRAMs differing in control system, such as the DDR-SDRAM and the FCRAM, on a device of the same device kind in order to meet various needs of users. In such a case, it becomes necessary to develop separate controllers respectively for the DDR-SDRAM and the FCRAM differing from each other in control system.
However, controllers must be developed respectively for different kinds of DRAMs in the same application device. When developing a device with RAMs that are different in control system mounted thereon in order to, for example, increase variations in the same device kind, therefore, the total time and labor required for the development is increased. Furthermore, in the conventional method, design and development of the controllers must be started after the specifications of the DRAMs have been completely fixed. In situations where the development cycles of application devices become short, like the present, therefore, a fear that the development will be delayed occurs. In addition, in the conventional method, it is difficult to flexibly cope with an alteration in DRAM specifications after the controllers have been developed once.